Chips / AI hardware Engineering Robotics AI jobs in Austin
AI roles at Austin AI companies, checked every night: every Austin role at AI-native companies, AI roles at AI-powered ones. Newest first, by the day we first saw them.
131 open roles · page 1 of 3
- Senior SRAM Engineer, Circuit DesignNVIDIA · First seen yesterday
- Senior Physical Design Methodology Engineer, PPA Improvement Technology ScalingNVIDIA · First seen yesterday
- Senior Systems Performance EngineerNVIDIA · First seen yesterday
- Electrical Engineer – Radio Frequency (RF) SystemsSaronic Technologies · Posted ~Aug 13, 2026
- Senior Electrical Engineer – Maritime Acoustic Sensor SystemsSaronic Technologies · Posted ~Apr 1, 2026
- Senior Verification Engineer - CPUNVIDIA · First seen 4 days ago
- Senior Compiler Engineer – GPU ComputeNVIDIA · First seen 9 days ago
- Power Architect - New College Grad 2027NVIDIA · First seen 9 days ago
- Senior Systems Software Engineer, CUDA and AI HW ProfilerNVIDIA · First seen 10 days ago
- AI Hardware ArchitectNVIDIA · First seen 12 days ago
- System Verification EngineerNVIDIA · First seen 12 days ago
- Senior System Verification EngineerNVIDIA · First seen 12 days ago
- Senior System Verification EngineerNVIDIA · First seen 12 days ago
- Senior GPU Compiler EngineerNVIDIA · First seen Oct 15, 2026
- AI GPU Power Architect - New College Grad 2026NVIDIA · First seen Oct 15, 2026
- System Software Engineer - PerformanceNVIDIA · First seen Oct 15, 2026
- Senior DTCO Engineer, CPU Physical DesignNVIDIA · First seen Oct 15, 2026
- Senior Full-Chip RTL Integration EngineerNVIDIA · First seen Oct 8, 2026
- Senior ASIC Verification EngineerNVIDIA · Posted ~Oct 5, 2026
- Senior Verification Engineer, SoCNVIDIA · Posted ~Oct 5, 2026
- GPU PCIe and Boot Architect - New College Grad 2027NVIDIA · Posted ~Oct 5, 2026
- PCIe Design Verification Intern - Summer 2027NVIDIA · Posted ~Oct 5, 2026
- Senior System Software Engineer - PerformanceNVIDIA · Posted ~Oct 5, 2026
- Senior DL Compiler Engineer - CUDA Tile LPUNVIDIA · Posted ~Oct 5, 2026
- ASIC Design Engineer – Clocks IPNVIDIA · Posted ~Oct 5, 2026
- Senior ASIC Design Engineer – Clocks IPNVIDIA · Posted ~Oct 5, 2026
- Senior Mask Layout Design EngineerNVIDIA · Posted ~Oct 5, 2026
- Senior Software Architect - Data Center SystemsNVIDIA · Posted ~Oct 5, 2026
- Senior ASIC Verification EngineerNVIDIA · Posted ~Oct 4, 2026
- Senior ASIC Timing EngineerNVIDIA · Posted ~Oct 4, 2026
- Senior Applied Power Architect - GPUNVIDIA · Posted ~Oct 4, 2026
- Senior Software Architect - Deep Learning and HPC CommunicationsNVIDIA · Posted ~Oct 4, 2026
- Principal Software Engineer, Rack-Scale System Software — CSP EngagementsNVIDIA · Posted ~Oct 3, 2026
- Senior Linux Kernel Systems Software Engineer – CSP EngagementsNVIDIA · Posted ~Oct 3, 2026
- Senior Physical Design Interposer EngineerNVIDIA · Posted ~Oct 1, 2026
- Senior ASIC Verification EngineerNVIDIA · Posted ~Oct 1, 2026
- Senior DFT EngineerNVIDIA · Posted ~Oct 1, 2026
- ASIC Design Engineer - HardwareNVIDIA · Posted ~Sep 30, 2026
- Senior DFT Engineer - Post SiliconNVIDIA · Posted ~Sep 30, 2026
- Senior Physical Design and Timing EngineerNVIDIA · Posted ~Sep 28, 2026
- GPU/SOC Low-Power Feature ArchitectNVIDIA · Posted ~Sep 28, 2026
- Senior Physical Design EngineerNVIDIA · Posted ~Sep 28, 2026
- ASIC Verification EngineerNVIDIA · Posted ~Sep 28, 2026
- Package Design Methodology EngineerNVIDIA · Posted ~Sep 28, 2026
- Senior ML Accelerator Engineer - GPUGeneral Motors · Posted ~Sep 27, 2026
- Senior ASIC Verification EngineerNVIDIA · Posted ~Sep 27, 2026
- ASIC Verification Engineer - New College Grad 2027NVIDIA · Posted ~Sep 27, 2026
- Principal Software Engineer, GPU Firmware and GPU System Software — CSP EngagementsNVIDIA · Posted ~Sep 23, 2026
- Senior Formal Verification EngineerNVIDIA · Posted ~Sep 22, 2026
- Principal System Power Management and Performance ArchitectNVIDIA · Posted ~Sep 22, 2026